The use of fast hopping frequency synthesizers is well known in the art for applications such as frequency hopping spread spectrum (FHSS) transmitters and receivers. In most transceivers, the synthesized frequency source (i.e. the local oscillator (LO)) is used to create the carrier signal in the transmitter and to down convert the signal in the receiver.
Local oscillator signals are normally generated using a phase locked loop (PLL) coupled to a crystal oscillator that provides the frequency reference. The loop bandwidth of the PLL determines its settling rate, as well as some of the phase noise properties of the generated local oscillator signal. The underlying trade off is that lower loop bandwidths may provide lower phase noise by better rejecting the high frequency phase noise of the PLL oscillator, but at a cost of longer settling times.
Some frequency synthesizers rely on a programmable PLL to control a voltage controlled oscillator (VCO) that produces desired output frequencies. A conventional, non-prepositioned PLL-type frequency synthesizer includes a phase comparator, a loop filter, a VCO, and a frequency divider all arranged in a loop, and a reference frequency source. Such an arrangement is shown in FIG. 1, which is also disclosed in U.S. Pat. No. 4,511,858, issued to Charavit et al. on Apr. 16, 1985.
As disclosed therein, frequency synthesizer 7 includes voltage-controlled oscillator (VCO) 1 for delivering an output frequency fN which is dependent on the control voltage VN applied thereto. The output of VCO 1 is connected to a frequency-divider circuit 2 which delivers an output signal at the frequency fN/N applied to phase comparator 3 to which is also applied a reference frequency fref. Phase comparator 3 delivers a signal whose average component is proportional to the phase difference existing between the two input signals applied to phase comparator 3. A low-pass filter 4 is connected to the output of comparator 3 for removing high frequency components of the spectrum of the output signal of the phase comparator. Finally, optional amplifier 5 is placed between filter 4 and VCO 1 in order to provide the loop gain and buffering of the phase control loop of synthesizer 7.
Since the switching time of synthesizer 7 is inversely proportional to the bandwidth of the loop, the switching time is preferably reduced by increasing the bandwidth.
A method for increasing the bandwidth may be provided by use of frequency pre-positioning, an example of which is shown by frequency synthesizer 12 in FIG. 2 (also disclosed by Charavit et al.). Frequency synthesizer 12 includes VCO 1, divider circuit 2 for dividing the output frequency fN which is controlled by control device 11, phase comparator 3 and frequency discriminator 6.
The frequency discriminator delivers a voltage proportional to the difference in frequencies applied as inputs to frequency discriminator 6. When the compared frequencies are identical, the discriminator does not deliver a control voltage. Rather, the control voltage is delivered by phase comparator 3. A summing amplifier 7 receives the signals from comparator 3 and discriminator 6 and delivers a signal which is filtered by low-pass filter 8.
In order to minimize the frequency deviation to be compensated by the control loop after a frequency switchover, pre-positioning voltage generator 9 is added to the loop in such a manner, as to position the VCO 1 as close as possible to the frequency to be delivered at the time of the frequency switchover. The frequency-switching control device 11 produces action both on divider circuit 2 and on voltage generator 9. Voltage generator 9 delivers a voltage VNP which, combined by summing circuit 10 with the voltage VNE delivered by filter 8, constitutes the control voltage VN of VCO 1.
Disadvantages of frequency synthesizer 12 are that it does not provide a high accuracy of positioning the output frequency of the synthesizer and does not provide a high rate of stabilizing (settling) the output frequency.
Referring next to FIG. 3, there is shown pre-positioned frequency synthesizer 80 disclosed in U.S. Pat. No. 6,714,085, issued on Mar. 30, 2004 to Bruce Alan Fette. Synthesizer 80 includes a reference frequency signal source 12 from which a reference signal 14 oscillating at a reference frequency is supplied. Reference frequency signal source 12 couples to a reference frequency divider 16. Frequency divider 16 is configured to produce a divided reference signal 18 oscillating at the reference frequency divided by M. Divided reference signal 18 couples to a first input of phase comparator 20. An output of phase comparator 20 provides a phase-error signal 22 and couples to an input of loop filter 24, which is configured to influence the bandwidth of phase-locked loop (PLL) 26.
As shown, the loop filter includes resistor 28 and capacitor 30 coupled to ground reference 34. A control signal 32 drives an input of variable frequency oscillator 36, whose output provides synthesizer-output signal 38.
Synthesizer-output signal 38 drives frequency divider 40, which is configured to divide the frequency of synthesizer-output signal 38 by N, producing a divided synthesizer-output signal 42. Divided synthesizer-output signal 42 is provided to phase comparator 20.
Control signal 32 also drives pre-positioning circuit 44. Pre-positioning circuit 44 causes synthesizer 80 to hop to new frequencies and to settle at these new frequencies.
Specifically, control signal 32 is routed to an input of filter-state-recording circuit 46. Filter-state-recording circuit 46 measures and records the various states exhibited by loop filter 24 as synthesizer 80 hops from frequency to frequency.
Filter-state-recording circuit 46 includes an analog-to-digital (A/D) conversion circuit 48 and read/write memory 50. The output of A/D conversion circuit 48 also couples to an input of controller 52, and an output of controller 52 couples to an address input of memory 50. A data output of memory 50 serves as the output for filter-state-recording circuit 46 and couples to an input of compensation circuit 54.
Compensation circuit 54 has an output coupled to an input of filter-state-assigning circuit 56, and filter-state-assigning circuit 56 has an output that drives control signal 32 from time to time. During these driving times, filter-state-assigning circuit 56 assigns states to loop filter 24, which causes loop-filter capacitor 30 to charge or discharge to desired voltage levels.
Filter-state-assigning circuit 56 includes multiplexer (MUX) 58. The compensation circuit output couples to an input of multiplexer 58. Outputs from controller 52 also couple to multiplexer 58. An output of multiplexer 58 couples to an input of a digital-to-analog (D/A) conversion circuit 60, and an output of D/A conversion circuit 60 couples to switching device 62. Switching device 62 also couples to loop filter 24, variable frequency oscillator 36, and filter-state-recording circuit 46. A selection input of switching device 62 couples to an output from controller 52.
The A/D conversion circuit 48 and D/A conversion circuit 60 have the same resolution, typically in the range of 8-16 bits. Compensation circuit 54 compensates for response differences between filter-state-recording circuit 46 and filter-state-assigning circuit 56. The response differences are due to offset differences and linearity differences between A/D conversion circuit 48 and D/A conversion circuit 60.
Pre-positioning circuit 44 seeks to record a given state of loop filter 24 during an earlier hop period in which a given synthesizer-output frequency is generated. Then, during a later hop period occurring the next time that same synthesizer-output frequency is to be generated, pre-positioning circuit 44 seeks to assign that same state to loop filter 24. But due, at least in part, to the response differences between filter-state-recording circuit 46 and filter-state-assigning circuit 56 error is inevitably introduced while recording the state during the earlier hop period, and additional error is introduced in reproducing the recorded state for assignment to loop filter 24 during the later hop period. Thus, compensation circuit 54 is provided to compensate for these errors.
In addition, compensation circuit 54 adapts to the individual characteristics of filter-state-recording circuit 46 and filter-state-assigning circuit 56. The adaptation is accomplished through a training process, whereby controller 52 trains compensation circuit 54 when synthesizer 80 is initially energized and on additional occasions while synthesizer 80 remains energized.
As will be explained, the present invention provides improvements over the frequency synthesizers shown in FIGS. 2 and 3.